High Performance SoC Architectures

• SoC Cryptographic Research (led by Dr M O'Neill (nee McLoone))
  • High-Speed Security Architectures
  • Generic Microprocessor Architectures for Cryptography
  • Wireless Ad Hoc Network Security Protocols & Architectures
  • Cryptography for Constrained Environments
  • Network Security Processing
  • Securing Cryptographic Architectures from Side Channel Attacks
    
• SoC architectures for Video and Signal Processing (led by Prof. J McCanny)
  • Programmable Processor Architectures for Modern Signal Processing Applications
  • Heterogeneous Architectures for Video Compression
• Network Processing (led by Dr S Sezer)
  • Re-configurable/programmable packet/frame processing
  • Web–Based collaborative design environment
  • WFQ packet scheduling architectures and computations for terabit networks
  • Parallel and scalable search, sort and lookup circuit architectures for network processing
  • Advanced packet buffer and shared buffer architectures
  • Adaptive, QoS aware scheduling for fixed wireless networks
       (Dr E Garcia, Dr S Sezer)
  • Hardware accelerated IP packet classification for terabit networks
  • Hardware accelerated deep packet inspection
  • Network security processing
       (Dr M O'Neill, Dr S Sezer)
  • Wireless Medium Access Control (MAC) algorithms and SoC processing architectures for SDMA and MIMO based wireless communication systems
       (Dr S Sezer, Dr E Garcia)

The following posters are available for download:

• SoC Cryptographic Research
• SoC architectures for Video and Signal Processing
• Network Processing